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general description the MAX19692 12-bit, 2.3gsps digital-to-analog converter(dac) enables direct digital synthesis of high-frequency and wideband signals in baseband and higher nyquist zones. it has been optimized for wideband communica- tions and radar applications. it has excellent spurious and noise performance and can be used for synthesis of wide- band signals in the frequency range from dc to more than 2ghz. the 2.3gsps update rate allows digital generation of signals with more than 1ghz bandwidth. the selectable frequency response enables signal output with high snr and excellent gain flatness in the first three nyquist zones, reducing the number of upconversion stages needed in a radio transmitter. with its unique ability to generate broad- band signals over a wide frequency range, the MAX19692 enables ultra-high data rate wire less modems and multi- standard software radio transmitters.the MAX19692 features an update rate up to 2.3gsps, and has four 12-bit multiplexed low-voltage differential signaling (lvds) input ports that each operate up to 575mhz. the device accepts a clock at the dac update rate that can be either a sine wave or a square wave. the input data rate is 1/4 the dac update rate. the MAX19692 provides an lvds data clock output to simpli- fy interfacing to fpga or asic devices. the MAX19692 has three frequency response output modes: non-return-to-zero (nrz) mode is the most common in the industry and provides highest dynamic rangeand output power in the 1st nyquist zone. return-to-zero (rz) mode trades off snr for improved gain flatness in the 1st, 2nd, and 3rdnyquist zones. radio frequency (rf) mode provides higher snr and excellent dynamic performance in the 2nd and3rd nyquist zones. the MAX19692 is a current-steering dac with an inte-grated, self-calibrated 50 differential output termina- tion to ensure optimum dynamic performance. theMAX19692 operates from 3.3v and 1.8v power sup- plies and consumes 760mw at 1.0gsps. a pplications MAX19692 12-bit, 2.3gsps, multi-nyquist dac with selectable frequency response ________________________________________________________________ maxim integrated products 1 ordering information 19-0517; rev 0; 6/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration appears at end of data sheet. evaluation kit available dac 4:1 registered mux MAX19692 12 clk rz rf bandgap reference clock divider /4 /8/16 clkdiv delay clkp clkn fsadj dacref refio 12 x 212 x 2 12 x 2 12 x 2 dap[11:0] dan[11:0] dbp[11:0] dbn[11:0] dcp[11:0] dcn[11:0] ddp[11:0] ddn[11:0] 2 dataclkp dataclkn outpoutn av dd3.3 av clk v dd1.8 gndcal refres frequency response select radar waveform andlo signal synthesis digital if generation in x-band transmitters arbitrary waveform generators direct digital synthesisautomatic test equipment direct digital generation of wideband rf signals up to 2ghz features ? industry-leading dynamic performance sfdr = 68dbc at f out = 1200mhz noise density = -162dbm/hz at 200mhz ? 1ghz signal bandwidth ? frequency response modes: nrz, rz, rf ? high snr and exceptional gain flatness innyquist zones 1, 2, 3 ? 4:1 multiplexed lvds inputs (up to 575mhz each) ? internal 50 differential output termination ? low power: 760mw (f clk = 1000mhz) ? compact 11mm x 11mm, 169 csbga package ? evaluation kit available (order MAX19692evkit) functional diagram 0 -5 -10-15 -20 -25 -30 -35 -40 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 f out normalized to dac update rate (f clk ) output amplitude response (db) nrz rz rf selectable frequency response part temp range package pkg code MAX19692exw-d -40? to +85? 169 csbga x16911-1 downloaded from: http:///
MAX19692 12-bit, 2.3gsps, multi-nyquist dac with selectable frequency response 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd3.3 to gnd, dacref ......................................-0.3v to +3.9v v dd1.8 , av clk to gnd, dacref ..........................-0.3v to +2.1v refio, fsadj to gnd, dacref ........-0.3v to (av dd3.3 + 0.3v) outp, outn to gnd, dacref ..........-0.3v to (av dd3.3 + 1.0v) cref to gnd, dacref............................-0.3v to (v dd1.8 + 0.3v) delay, clkdiv, rz, rf, refres, cal to gnd, dacref ......................-0.3v to (av dd3.3 + 0.3v) clkp, clkn to gnd, dacref..............-0.3v to (av clk + 0.3v) dap0?ap11, dbp0?bp11, dcp0?cp11 to gnd, dacref........-0.3v to (v dd1.8 + 0.3v) ddp0?dp11 to gnd, dacref............-0.3v to (v dd1.8 + 0.3v) dan0?an11, dbn0?bn11, dcn0?cn11 to gnd, dacref.......-0.3v to (v dd1.8 + 0.3v) ddn0?dn11 to gnd, dacref...........-0.3v to (v dd1.8 + 0.3v) dataclkp, dataclkn to gnd, dacref .....................................................-0.3v to (v dd1.8 + 0.3v) dataclkp, dataclkn continuous current ......................8ma continuous power dissipation (t a = +70?) 169-pin csbga (derate 33.3mw/? above +70?)..........................................................2666.7mw thermal resistance ja (note 1)...................................+18?/w operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-60? to +150? electrical characteristics(av dd3.3 = 3.3v, v dd1.8 = av clk = 1.8v, r refres = 500 , r set = 2k , v refio = external 1.25v, cal on, nrz mode, transformer- coupled differential output, i out = 20ma, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units static performance resolution 12 bits integral nonlinearity inl measured differentially ?.3 lsb differential nonlinearity dnl measured differentially ?.9 lsb offset voltage error os measured differentially, no external load resistors -0.5 ?.1 +0.5 %fs offset drift ?0 ppm/ c full-scale outputcurrent i out (note 3) 8 20 ma output-current gainerror ge -4 +4 %fs internal reference -0.003 output-voltage gaindrift external reference -0.0025 db/ c maximum outputpower p out differential, into 50 load -2.6 dbm output resistance r out differential, cal 0.7 x av dd3.3 (note 4) 44 48 52 dynamic performance (note 5) minimum outputupdate rate f clk 10 mhz maximum outputupdate rate f clk 1.8v v dd1.8 1.9v 2300 mhz wideband noise-spectral density f clk = 1000mhz, f out = 200mhz, -12dbfs -162 d bm /h z note 1: thermal resistance based on a 4.5in x 5.5in multilayer board. downloaded from: http:///
MAX19692 12-bit, 2.3gsps, multi-nyquist dac with selectable frequency response _______________________________________________________________________________________ 3 electrical characteristics (continued)(av dd3.3 = 3.3v, v dd1.8 = av clk = 1.8v, r refres = 500 , r set = 2k , v refio = external 1.25v, cal on, nrz mode, transformer- coupled differential output, i out = 20ma, t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 2) parameter symbol conditions min typ max units f out = 50mhz, -6dbfs, nrz mode 73 f ou t = 100m h z, - 6d bfs , n rz m od e7 4 f ou t = 200m h z, - 6d bfs , n rz m od e7 0 f ou t = 400m h z, - 6d bfs , rf m od e7 1 f clk = 500mhz f out = 600mhz, -6dbfs, rf mode 73 f ou t = 200m h z, - 6d bfs , n rz m od e7 5 f ou t = 409m h z, - 0.1d bfs , n rz m od e, t a + 25 c 60 68 f ou t = 409m h z, - 0.1d bfs , n rz m od e 56 68 f out = 800mhz, -6dbfs, rf mode 67 f clk = 1000mhz f ou t = 1200m h z, - 6d bfs , rf m od e6 5 f ou t = 100m h z, - 6d bfs 71 f ou t = 200m h z, - 6d bfs 68 f ou t = 400m h z, - 6d bfs 70 f c lk = 2000m h z, n rz m od e f ou t = 800m h z, - 6d bfs 58 spurious-freedynamic range within nyquist zone of f ou t sfdr f c lk = 2300m h z, n rz m od e f ou t = 92m h z, 0d bfs 60 71 dbc f out1 = 200mhz, -7dbfs f clk = 1000mhz, nrz mode f out2 = 201mhz, -7dbfs -72 f out1 = 1300mhz, -7dbfs 2-tone imd ttimd f clk = 1000mhz, rf mode f out2 = 1301mhz, -7dbfs -66 dbc minimum outputbandwidth bw -3db (note 6) 1500 mhz reference internal referencevoltage range v refio 1.1 1.2 1.3 v reference inputcompliance range v refiocr 0.50 1.25 v reference inputresistance r refio 10 k reference voltage drift tco ref 50 ppm/ c analog output timing (note 7) output fall time t fall 90% to 10% 270 ps output rise time t rise 10% to 90% 270 ps settling to 0.1% 3.5 settling time t s settling to 0.025% 4.5 ns output propagationdelay t pd (note 8) 0.9 ns downloaded from: http:///
MAX19692 12-bit, 2.3gsps, multi-nyquist dac with selectable frequency response 4 _______________________________________________________________________________________ electrical characteristics (continued)(av dd3.3 = 3.3v, v dd1.8 = av clk = 1.8v, r refres = 500 , r set = 2k , v refio = external 1.25v, cal on, nrz mode, transformer- coupled differential output, i out = 20ma, t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 2) parameter symbol conditions min typ max units timing characteristics data to clock setuptime t setup referenced to rising edge of data clock (note 9) 1.6 ns data to clock holdtime t hold referenced to rising edge of data clock (note 9) -0.8 ns data latency (note 10) 14 clock cycles lvds logic inputs (dap11 dap0, dan11 dan0, dbp11 dbp0, dbn11 dbn0, dcp11 dcp0, dcn11 dcn0, ddp11 ddp0, ddn11 ddn0) differential inputlogic-high v ih 100 mv differential inputlogic-low v il -100 mv common-modevoltage range v com 1.125 1.375 v differential inputresistance r in 85 125 input capacitance c in 1.5 pf cmos logic inputs (rz, rf, clkdiv, delay) input logic-high v ih 0.7 x av dd3.3 v input logic-low v il 0.3 x av dd3.3 v input leakage current i in -15 +15 ? input capacitance c in 3p f clock inputs (clkp, clkn) f clk 1.5ghz 0.6 mi nim um differ ential input v oltag e s w ing ( n ote 11) v clk f clk = 2.3ghz, see figure 6 for dependence on f clk 2.0 v p-p maximum differentialvoltage swing v clk (note 11) 2.5 v p-p differential inputslew rate sr clk 6000 v/? common-modevoltage range v comclk 0.55 av c lk / 3 0.65 v input resistance r clk differential 100 input capacitance c clk 2p f downloaded from: http:///
MAX19692 12-bit, 2.3gsps, multi-nyquist dac with selectable frequency response _______________________________________________________________________________________ 5 electrical characteristics (continued)(av dd3.3 = 3.3v, v dd1.8 = av clk = 1.8v, r refres = 500 , r set = 2k , v refio = external 1.25v, cal on, nrz mode, transformer- coupled differential output, i out = 20ma, t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 2) parameter symbol conditions min typ max units data clock outputs (dataclkp, dataclkn) differential output v dclk with 100 differential termination ?.25 ?.35 ?.45 v output rise andfall time t r , t f with 100 differential termination 0.5 ns common-modevoltage range v com 1.125 1.25 1.375 v output resistance r clk differential 100 power supplies analog-supply voltagerange av dd3.3 3.1 3.3 3.5 v 10mhz f clk < 2.0ghz (note 9) 1.7 1.8 1.9 1.8v supply voltagerange v dd1.8 2.0ghz f clk 2.3ghz 1.8 1.9 v 10mhz f clk < 2.0ghz (note 9) 1.7 1.8 1.9 clock-supply voltagerange av clk 2.0ghz f clk 2.3ghz 1.8 1.9 v analog supplycurrent i avdd3.3 f clk = 1000mhz, f out = 10mhz, a out = 0dbfs 107 117 ma digital supply current i vdd1.8 f clk = 1000mhz, f out = 10mhz, a out = 0dbfs 61 76 ma clock supply current i avclk f clk = 1000mhz, f out = 10mhz, a out = 0dbfs 164 191 ma total p ow er d i ssi p ati on p diss f clk = 1000mhz, f out = 10mhz, a out = 0dbfs 760 870 mw note 2: all specifications are 100% tested at t a +25 c. specifications at t a < +25 c are guaranteed by design and characterization. note 3: nominal full-scale current i out = 32 x i ref . note 4: r out can be set to 50 as described in the output resistor calibration section. note 5: clk input = +10dbm, ac-coupled sine wave. note 6: excludes impulse-response dependent rolloff inherent in the dac. measured single-ended into 50 termination resistor. note 7: measured differentially into a 50 termination resistor. note 8: excludes data latency. note 9: guaranteed by design and characterization. note 10: da_p/da_n to dac output. note 11: differential voltage swing defined as ? v p ? + ? v n ? . v clkn v clkp v p v n downloaded from: http:///
MAX19692 12-bit, 2.3gsps, multi-nyquist dac with selectable frequency response 6 _______________________________________________________________________________________ sfdr vs. output frequency f clk = 500mhz, nrz mode f out (mhz) sfdr (dbc) MAX19692 toc01 0 50 100 150 200 250 30 40 50 60 70 80 0dbfs -3dbfs -6dbfs sfdr vs. output frequency f clk = 1000mhz, nrz mode f out (mhz) sfdr (dbc) MAX19692 toc02 0 100 200 300 400 500 30 40 50 60 70 80 0dbfs -3dbfs -6dbfs sfdr vs. output frequency f clk = 1500mhz, nrz mode f out (mhz) sfdr (dbc) MAX19692 toc03 0 125 250 375 500 625 750 30 40 50 60 70 80 0dbfs -6dbfs -3dbfs sfdr vs. output frequency f clk = 2300mhz, nrz mode f out (mhz) sfdr (dbc) MAX19692 toc04 0 230 460 690 920 1150 30 40 50 60 70 80 0dbfs -6dbfs -3dbfs sfdr vs. output frequency f clk = 500mhz, rz mode f out (mhz) sfdr (dbc) MAX19692 toc05 0 50 100 150 200 250 30 40 50 60 70 80 0dbfs -6dbfs -3dbfs sfdr vs. output frequency f clk = 1000mhz, rz mode f out (mhz) sfdr (dbc) MAX19692 toc06 0 100 200 300 400 500 30 40 50 60 70 80 -3dbfs -6dbfs 0dbfs sfdr vs. output frequency f clk = 1500mhz, rz mode f out (mhz) sfdr (dbc) MAX19692 toc07 0 125 250 375 500 625 750 30 40 50 60 70 80 -3dbfs 0dbfs -6dbfs sfdr vs. output frequency f clk = 2300mhz, rz mode f out (mhz) sfdr (dbc) MAX19692 toc08 0 230 460 690 920 1150 30 40 50 60 70 80 0dbfs -3dbfs -6dbfs sfdr vs. output frequency f clk = 500mhz, rz mode f out (mhz) sfdr (dbc) MAX19692 toc09 250 300 350 400 450 500 30 40 50 60 70 80 -6dbfs -3dbfs 0dbfs typical operating characteristics (av dd3.3 = 3.3v, av dd1.8 = dv dd = av clk = 1.8v, r refres = 500 , r set = 2k , v refio = external 1.25v, cal on, transformer- coupled differential output, i out = 20ma, t a = +25 c, unless otherwise noted.) downloaded from: http:///
MAX19692 12-bit, 2.3gsps, multi-nyquist dac with selectable frequency response _______________________________________________________________________________________ 7 sfdr vs. output frequency f clk = 1000mhz, rz mode f out (mhz) sfdr (dbc) MAX19692 toc10 500 600 700 800 900 1000 30 40 50 60 70 80 -3dbfs -6dbfs 0dbfs sfdr vs. output frequency f clk = 1500mhz, rz mode f out (mhz) sfdr (dbc) MAX19692 toc11 750 875 1000 1125 1250 1375 1500 30 40 50 60 70 80 -3dbfs 0dbfs -6dbfs sfdr vs. output frequency f clk = 500mhz, rf mode f out (mhz) sfdr (dbc) MAX19692 toc12 250 300 350 400 450 500 30 40 50 60 70 80 0dbfs -3dbfs -6dbfs sfdr vs. output frequency f clk = 1000mhz, rf mode f out (mhz) sfdr (dbc) MAX19692 toc13 500 600 700 800 900 1000 30 40 50 60 70 80 -3dbfs -6dbfs 0dbfs sfdr vs. output frequency f clk = 1500mhz, rf mode f out (mhz) sfdr (dbc) MAX19692 toc14 750 875 1000 1125 1250 1375 1500 30 40 50 60 70 80 -3dbfs 0dbfs -6dbfs sfdr vs. output frequency f clk = 2000mhz, rf mode f out (mhz) sfdr (dbc) MAX19692 toc15 1000 1200 1400 1600 1800 2000 30 40 50 60 70 80 -6dbfs 0dbfs -3dbfs sfdr vs. output frequency f clk = 500mhz, rz mode f out (mhz) sfdr (dbc) MAX19692 toc16 500 550 600 650 700 750 30 40 50 60 70 80 0dbfs -6dbfs -3dbfs sfdr vs. output frequency f clk = 1000mhz, rz mode f out (mhz) sfdr (dbc) MAX19692 toc17 1000 1100 1200 1300 1400 1500 30 40 50 60 70 80 0dbfs -6dbfs -3dbfs sfdr vs. output frequency f clk = 500mhz, rf mode f out (mhz) sfdr (dbc) MAX19692 toc18 500 550 600 650 700 750 30 40 50 60 70 80 -6dbfs -3dbfs 0dbfs typical operating characteristics (continued) (av dd3.3 = 3.3v, av dd1.8 = dv dd = av clk = 1.8v, r refres = 500 , r set = 2k , v refio = external 1.25v, cal on, transformer- downloaded from: http:///
MAX19692 12-bit, 2.3gsps, multi-nyquist dac with selectable frequency response 8 _______________________________________________________________________________________ typical operating characteristics (continued) (av dd3.3 = 3.3v, av dd1.8 = dv dd = av clk = 1.8v, r refres = 500 , r set = 2k , v refio = external 1.25v, cal on, transformer- coupled differential output, i out = 20ma, t a = +25 c, unless otherwise noted.) sfdr vs. output frequency f clk = 1000mhz, rf mode f out (mhz) sfdr (dbc) MAX19692 toc19 1000 1100 1200 1300 1400 1500 30 40 50 60 70 80 0dbfs -3dbfs -6dbfs sfdr vs. output amplitude f clk = 1000mhz, f out = 200mhz a out (dbfs) sfdr (dbc) MAX19692 toc20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 0 10 20 30 40 50 60 70 80 rz mode nrz mode sfdr vs. output amplitude f clk = 1000mhz, f out = 800mhz a out (dbfs) sfdr (dbc) MAX19692 toc21 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 0 10 20 30 40 50 60 70 80 rz mode rf mode sfdr vs. output amplitude f clk = 1000mhz, f out = 1200mhz a out (dbfs) sfdr (dbc) max19296 toc22 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 0 10 20 30 40 50 60 70 80 rz mode rf mode two-tone imd vs. output frequency f clk = 500mhz, 1mhz spacing, nrz mode f out (mhz) imd (dbc) MAX19692 toc23 0 50 100 150 200 250 -80 -70 -60 -50 -40 -30 a tone = -12dbfs a tone = -6dbfs two-tone imd vs. output frequency f clk = 1000mhz, 1mhz spacing, nrz mode f out (mhz) imd (dbc) max19262 toc24 0 100 200 300 400 500 -80 -70 -60 -50 -40 -30 a tone = -12dbfs a tone = -6dbfs two-tone imd vs. output frequency f clk = 1000mhz, 1mhz spacing, rf mode f out (mhz) imd (dbc) MAX19692 toc25 500 600 700 800 900 1000 -80 -70 -60 -50 -40 -30 a tone = -12dbfs a tone = -6dbfs two-tone imd vs. output frequency f clk = 1000mhz, 1mhz spacing, rf mode f out (mhz) imd (dbc) MAX19692 toc26 1000 1100 1200 1300 1400 1500 -80 -70 -60 -50 -40 -30 a tone = -12dbfs a tone = -6dbfs clk feedthrough vs. clk frequency f out = 200mhz, a out = -1dbfs, nrz mode f clk (mhz) a clk (dbm) MAX19692 toc27 500 800 1100 1400 1700 2000 2300 -90 -80 -70 -60 -50 -40 +85 c +25 c -40 c downloaded from: http:///
MAX19692 12-bit, 2.3gsps, multi-nyquist dac with selectable frequency response _______________________________________________________________________________________ 9 output noise density vs. clk frequency f out = 200mhz, nrz mode f clk (mhz) noise density (dbm/hz) max19296 toc28 500 750 1000 1250 1500 1750 2000 -180 -170 -160 -150 -140 -130 0dbfs -6dbfs -12dbfs sfdr spectral plot f clk = 1600mhz, f out = 700mhz, a out = -3dbfs, nrz mode MAX19692 toc29 span = 800mhz, center = 400mhz, rbw = 20khz power (dbm) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 700mhz at -11.5dbm hd2 at -62dbc hd3 at -62dbc two-tone imd spectral plot f clk = 1600mhz, f out = 695mhz, f out2 = 705mhz MAX19692 toc30 center = 700mhz, span = 100mhz, rbw = 3khz power (dbm) -100 -90 a out1 = -9dbfs a out2 = -9dbfs -80 -70 -60 -50 -40 -30 -20 -10 -110 imd products imd products worst case at -60dbc sfdr spectral plot, 3rd nyquist zone f clk = 1000mhz, f out = 1290mhz, a out = -3dbfs, rf mode MAX19692 toc31 span = 500mhz, center = 1250mhz, rbw = 30khz power (dbm) -100 -90 1290mhz at -17.5dbm -80 -70 -60 -50 -40 -30 -20 -10 -110 clk + clk/4 at -63dbc hd2 at -66dbc clk sfdr vs. temperature f clk = 1000mhz, f out = 200mhz, nrz mode temperature ( c) sfdr (dbc) MAX19692 toc32 -40 -15 10 35 60 85 30 40 50 60 70 80 0dbfs -6dbfs -3dbfs sfdr vs. temperature (av dd3.3 , 1.8v supplies) f clk = 2000mhz, f out = 400mhz, nrz mode temperature ( c) sfdr (dbc) MAX19692 toc33 -40 -15 10 35 60 85 40 50 60 70 80 90 100 3.5v, 1.9v 3.5v, 1.7v 3.1v, 1.9v 3.1v, 1.7v a out = 0dbfs 3.1v, 1.9v sfdr vs. temperature (av dd3.3 , 1.8v supplies) f clk = 2000mhz, f out = 400mhz, nrz mode temperature ( c) sfdr (dbc) mMAX19692 toc34 -40 -15 10 35 60 85 65 66 67 68 69 70 71 72 73 74 75 3.5v, 1.9v 3.5v, 1.7v 3.1v, 1.9v 3.1v, 1.7v a out = -3dbfs sfdr vs. temperature (av dd3.3 , 1.8v supplies) f clk = 2000mhz, f out = 400mhz, nrz mode temperature ( c) sfdr (dbc) MAX19692 toc35 -40 -15 10 35 60 85 65 66 67 68 69 70 71 72 73 74 75 3.5v, 1.9v 3.5v, 1.7v 3.1v, 1.9v 3.1v, 1.7v a out = -6dbfs typical operating characteristics (continued) (av dd3.3 = 3.3v, av dd1.8 = dv dd = av clk = 1.8v, r refres = 500 , r set = 2k , v refio = external 1.25v, cal on, transformer- coupled differential output, i out = 20ma, t a = +25 c, unless otherwise noted.) downloaded from: http:///
MAX19692 12-bit, 2.3gsps, multi-nyquist dac with selectable frequency response 10 ______________________________________________________________________________________ integral nonlinearity vs. digital code digital code inl(lsb) MAX19692 toc37 0 512 1024 1536 2048 2560 3072 3584 4096 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 differential nonlinearity vs. digital code digital code dnl (lsb) MAX19692 toc38 0 512 1024 1536 2048 2560 3072 3584 4096 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 supply current vs. clk frequency f out = 100mhz, a out = 0dbfs, nrz mode f clk (mhz) current (ma) MAX19692 toc39 500 800 1100 1400 1700 2000 2300 75 125 175 225 275 325 375 425 475 525 575 1.8v rz mode 1.8v nrz and rf modes 3.3v typical operating characteristics (continued) (av dd3.3 = 3.3v, av dd1.8 = dv dd = av clk = 1.8v, r refres = 500 , r set = 2k , v refio = external 1.25v, cal on, transformer- coupled differential output, i out = 20ma, t a = +25 c, unless otherwise noted.) internal reference (refio) voltage vs. temperature temperature ( c) v refio (v) MAX19692 toc36 -40 -15 10 35 60 85 1.10 1.12 1.14 1.16 1.18 1.20 1.22 1.24 1.26 1.28 1.30 downloaded from: http:///
MAX19692 12-bit, 2.3gsps, multi-nyquist dac with selectable frequency response ______________________________________________________________________________________ 11 pin name function a1 refio reference input/output. output pin for the internal 1.2v-bandgap reference. refio has a 10k series resistance and can be driven using an external reference. connect a 1? capacitor between refio and dacref. a2 fsadj full-scale adjust input. sets the full-scale output current of the dac. for a 20ma full-scale output current, connect a 2k resistor between fsadj and dacref. a3 dacref current-set resistor return path. for a 20ma full-scale output current, connect a2k resistor between fsadj and dacref. dacref is internally connected to agnd. do not connect to external ground. a4, a5, a7, a9 av dd3.3 analog 3.3v supply voltage. accepts a 3.1v to 3.5v supply voltage range. connect47nf bypass capacitors between each av dd3.3 pin and agnd. a6 outp positive terminal of differential dac output. outp has a calibrated internal 25 resistor to av dd3.3 . a8 outn negative terminal of differential dac output. outn has a calibrated internal 25 resistor to av dd3.3 . a10, b10, c2, c3, c10, e1 e4, e10 e13, f13 v dd1.8 analog 1.8v supply voltage. accepts a 1.7v to 1.9v supply voltage range. connect47nf bypass capacitors between each v dd1.8 pin and gnd. a11, a13, b5 b9, b11, c4 c9, c11, d1 d11, d13, e5 e9, g13, m13 gnd ground. connect to ground plane with minimum inductance. a12, b12, c12, d12 av clk clock 1.8v supply voltage. accepts a 1.7v to 1.9v supply voltage range. connect47nf bypass capacitors between av clk and gnd. b1 cref noise bypass pin. a 1? capacitor between the cref and dacref band limits thephase noise of the MAX19692. b2 refres calibration reference resistor input. connect a 500 resistor between refres and av dd3.3 . the internal analog output resistors are calibrated to this external resistor. b3 rz return-to-zero (rz) mode-select input.rz = 0 (and rf = 0): normal dac (nrz) operation (default). rz = 1 (and rf = 0): return-to-zero (rz) dac operation. rz is a 3.3v cmos logic input with an internal pulldown resistor. b4 rf radio frequency (rf) mode-select input.rf = 0: nrz or rz dac operation. rf = 1 (and rz = 0): rf dac operation. rf is a 3.3v cmos logic input with internal pulldown resistor. c13 clkp lvds-compatible converter clock input. there is an internal 100 termination resistor between clkp and clkn. b13 clkn lvds-compatible converter clock input. there is an internal 100 termination resistor between clkp and clkn. c1 cal dac output resistance calibration input.calibration of the internal output resistors is initiated by a rising edge on cal. cal = 1: output resistors are calibrated. cal = 0: output resistors are uncalibrated. cal is a 3.3v cmos input with an internal pulldown resistor. leakage current is less than ?5?. pin description downloaded from: http:///
MAX19692 12-bit, 2.3gsps, multi-nyquist dac with selectable frequency response 12 ______________________________________________________________________________________ detailed description the MAX19692 is a high-performance, high-speed, 12-bitcurrent-steering dac with an integrated 50 differential output termination. the dac is capable of operating withclock speeds up to 2.3ghz. the converter consists of an edge-triggered 4:1 input data multiplexer followed by a current-steering circuit. this circuit is capable of generat- ing differential full-scale currents in the 8ma to 20ma range. internal 25 resistors on each output, in combina- tion with an external termination, convert the differentialcurrent into a voltage. the internal resistors are terminat- ed to the 3.3v analog supply, av dd3.3 . the internal termi- nation resistors can be calibrated to an external 500 precision resistor. a calibration cycle can be run everytime the converter is powered up, or at any other time. an integrated 1.2v-bandgap reference, control amplifier, and user-selectable external resistor determine the data con- verter s full-scale range. the converter features selectable frequency response to allow application-dependent opti-mization of output power and gain flatness. three responses can be selected: non-return-to-zero (nrz), return-to-zero (rz), or radio frequency (rf). reference input/output the MAX19692 supports operation with the on-chip 1.2v-bandgap reference or an external reference voltage source. refio serves as the input for an external, low- impedance reference source, and as the output if the dac is operating with the internal reference. for stable operation with the internal reference, refio should be decoupled to dacref with a 1? capacitor. refio must be buffered with an external amplifier if heavier loading is required, due to its 10k series resistance. the MAX19692 s reference circuit (figure 1) employs a control amplifier, designed to regulate the full-scale cur-rent i out for the differential current outputs of the dac. the output current can be calculated as follows: i out = 32 x i ref x 4095/4096 where i ref is the reference output current (i ref = v refio / r set ) and i out is the full-scale output current of the dac. located between fsadj and dacref,r set is typically set to 2k , which results in a full-scale current of 20ma if the internal reference is used. pin name function f6 f3, f1, f2, h6 h1 dap11 dap0 positive terminals of a-channel lvds data inputs. dap11 is msb.offset binary format. g6 g3, g1, g2, j6 j1 dan11 dan0 negative terminals of a-channel lvds data inputs k1 k4, m1 m4, k5, m5, k6, m6 dbp11 dbp0 positive terminals of b-channel lvds data inputs. dbp11 is msb.offset binary format. l1 l4, n 1 n4, l5, n5, l6, n6 dbn11 dbn0 negative terminals of b-channel lvds data inputs m7, k7, m8, k8, m9 m12, k9, k10, k11, l12 dcp11 dcp0 positive terminals of c-channel lvds data inputs. dcp11 is msb.offset binary format. n7, l7, n8, l8, n9 n12, l9, l10, l11, k12 dcn11 dcn0 negative terminals of c-channel lvds data inputs g7, j7, j12 j8, g12 g8 ddp11 ddp0 positive terminals of d-channel lvds data inputs. ddp11 is msb.offset binary format. f7, h7, h12 h8, f12 f8 ddn11 ddn0 negative terminals of d-channel lvds data inputs j13 dataclkp positive terminal of lvds data output clock h13 dataclkn negative terminal of lvds data output clock k13 delay data clock delay mode input.adjusts the delay of the output data clock. delay = 0: no delay added. delay = 1: add delay of 1/2 input data period (2 dac clock cycles). delay is a 3.3v cmos input with an internal pulldown resistor. l13 clkdiv data clock divide mode input.clkdiv = 1: data clock rate = input data rate / 2 (f clk / 8). clkdiv = 0: data clock rate = input data rate / 4 (f clk / 16). clkdiv is a 3.3v cmos input with an internal pulldown resistor. n13 n.c. no connection. this pin should be left unconnected. pin description (continued) downloaded from: http:///
MAX19692 12-bit, 2.3gsps, multi-nyquist dac with selectable frequency response ______________________________________________________________________________________ 13 analog outputs the MAX19692 is a differential current-steering dacwith built-in self-calibrated output termination resistors to optimize performance. the outputs are terminated to av dd3.3 , and are calibrated to provide a 50 differen- tial output resistance. in addition to the signal current, aconstant 10ma current sink is connected to each dac output. typically, the outputs should be used with a 50 transformer. if the transformer is center tapped, it is recommended that the center tap be connected toav dd3.3 . if the transformer is not center tapped, bias tees or rf chokes can be used to pull up the outputs.figure 2 shows an equivalent circuit of the internal out- put structure of the MAX19692. the termination resistors, r t , are calibrated to 23.5 . r m = r m1 +r m2 +r m3 is resistance associated with the dac output traces and bond wires, and is not cali-brated. the output resistance is equal to 2r t + 2r m , and is nominally 50 . the MAX19692 is normally used with an external differential 50 load, r l . for this case, the peak differential output voltage is calculated as:where i out is the full-scale current, which is typically set to 20ma. with r l = 50 , r t = 23.5 , and r m = 1.5 , v out = 0.235v is found. this corresponds to an output power of -2.6dbm. as shown in figure 2, the output cir-cuit has some resistive, capacitive, and inductive ele- ments. these elements limit the output bandwidth to 2ghz with a resistive differential 50 load. output resistor calibration the integrated termination resistors, r t , must be cali- brated to have an accurately known dac output resis-tance and an accurately known dac output voltage. vi rr out out lt lmt = ++ rr r 22 av dd3.3 r t = 23.5 r t = 23.5 r m1 = 0.6 r m2 = 0.4 r m3 = 0.5 r m1 = 0.6 r m2 = 0.4 r m3 = 0.5 50 3pf 3pf 0.75pf 0.4pf 0.4pf 0.5pf outn outp 0.5pf 0.3nh 0.3nh 0.3nh 0.3nh 1.3nh1.3nh 10ma + i fs x (4095 - code) / 4096 10ma + i fs x code / 4096 figure 2. equivalent output circuit r set i ref = v refio / r set refio fsadj dacref outp outn current- source array dac 10k MAX19692 1.2v reference i ref 1 f figure 1. reference architecture, internal reference configuration downloaded from: http:///
MAX19692 12-bit, 2.3gsps, multi-nyquist dac with selectable frequency response 14 ______________________________________________________________________________________ the termination resistors are calibrated to the externalreference resistor, r refres , which should be connect- ed between refres (pin b2) and av dd3.3 . r refres is nominally 500 . a plot showing the typical relation between the dac output resistance and r refres is shown in figure 3.the calibration cycle is initiated with a rising edge on the cal pin. the cal pin must be asserted after the supply voltages and the reference voltage have reached steady state. input data should not be switch- ing while calibration is running. the duration of the cali- bration cycle is shorter than 65,536 dac clock cycles which is less than 65.6? if the converter is operated with a 1ghz clock rate. the cal pin must beheld high for the output resistors to remain calibrated. if the clock is stopped, or if power is cycled, a new cali- bration cycle must be run. dac impulse/frequency response selection the MAX19692 has three impulse/frequency responsemodes. these are set with the rz and rf input pins as described in table 1. the impulse responses of the three operating modes are shown in figure 4. the sample period is equal to t. the default operating mode of the MAX19692 is nrz mode. the sinc (sine(x)/x) response has zeros at every multiple of the dac update frequency f clk = 1/t. using this impulse response, the frequency response of thedac has the familiar sinc shape: where f out is the dac output frequency, t = 1/f clk is the period of the dac clock, and a 0 is the peak low-fre- quency output amplitude.in rz mode, the dac output has a 50% duty cycle. the dac output stays at midscale for the remaining 50% of the clock cycle. the resulting frequency response is: a a 2 t / 2 t / 2 rz 0 out out = ?? ? ?? ? sin( ) f f aa t t nrz 0 out out = ?? ? ?? ? sin( ) f f 44 4746 45 4948 5150 52 5453 55 450 470 480 490 460 500 510 520 540 530 550 refres ( ) r out ( ) figure 3. output resistance vs. refres resistor rz rf frequency response mode 0 0 nrz 10 r z 01 r f 1 1 do not use table 1. rz and rf input truth table -t/2 (a) t/2 (b) -t/2 t/2 (c) -t/2 t/2 figure 4. impulse responses in (a) nrz mode, (b) rz mode, and (c) rf mode downloaded from: http:///
MAX19692 12-bit, 2.3gsps, multi-nyquist dac with selectable frequency response ______________________________________________________________________________________ 15 this frequency response is flatter than the nrzresponse in the three first nyquist zones, particularly in the 2nd and 3rd nyquist zones making this dac usable for outputting wideband signals in the 2nd and3rd nyquist zones. the third mode of operation is the rf mode. in this mode, the dac output response is inverted in the sec- ond half of the clock cycle, resulting in a doublet pulse at the output of the dac in every clock cycle. the resulting dac frequency response is: the rf mode increases the dac output power in the sec- ond and third nyquist zones and attenuates it in the first nyquist zone. the frequency responses for the three modes of opera- tion are plotted in figure 5. nrz mode provides the highest power in the first nyquist zone. rz mode provides the flattest frequency response in the first and third nyquist zones, and rf mode provides superior output power in the second and third nyquist zones, as well as the flattest gain in the second nyquist zone. clock inputs the MAX19692 features a flexible differential clockinput (clkp, clkn) operating from a separate supply (av clk ) to achieve the best possible jitter performance. the two clock inputs can be driven from a single-endedor a differential clock source. a sine wave or a square wave can be used. for single-ended operation, clkp should be driven by a logic source, while clkn should be bypassed to gnd with a 0.1? capacitor. driving the clocks differentially is recommended for opti- mum jitter performance. choose a clock amplitude that is as large as possible (without the clock voltage at the clkn and clkp pins going more than 200mv below ground or above the av clk supply voltage) to minimize jitter. this results in the most accurate duty cycle and hence the most accurate gain in rz and rf modes. foran ac-coupled, differential sine-wave clock, the clock amplitude should not be higher than 2.5v peak-to-peak (12dbm if terminated in 50 ). the typical performance plots in this data sheet have generally been measuredusing a 10dbm (2v p-p ) clock amplitude. the MAX19692 can be used with a sinusoidal clockamplitude as low as 0.6v p-p below 1.5gsps. for higher update rates, the clock amplitude should stay within theoperating region specified in figure 6. the clkp and clkn pins are internally biased to 0.6v with resistors. this allows the user to ac-couple clock sources directly to the device without external resistors to define the dc level. aa t / 2 t / 2 t / 2 rf 0 out out out = ?? ? ?? ? sin( ) sin( ) f f f 0 -5 -10-15 -20 -25 -30 -35 -40 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 f out normalized to dac update rate (f clk ) output amplitude response (db) nrz rz rf selectable frequency response figure 5. amplitude responses for nrz mode (solid line), rz mode (dash-dot line), and rf mode (dashed line). excludes output bandwidth limitation. dac update rate (gsps) 0.5 1.0 1.5 2.0 2.3 peak-to-peak differential sinusoidal clock voltage (v) 2.52.0 1.5 1.0 0.5 [2.3gsps, 2.0v] 2.5v max valid operating region 0.6v min [1.5gsps, 0.6v] figure 6. recommended clock amplitude downloaded from: http:///
MAX19692 12-bit, 2.3gsps, multi-nyquist dac with selectable frequency response 16 ______________________________________________________________________________________ the MAX19692 has an internal 100 termination resis- tor between clkp and clkn. an extra 100 differen- tial termination resistor should be added if using a 50 clock source. see figure 7 for a convenient and quickway to apply a differential signal created from a single- ended source and a wideband transformer. the clock circuit in figure 7 has some amplitude asym- metry at update rates above 1gsps, due to transformer loss. this may cause performance degradation for some operating conditions. a clock interface circuit with improved symmetry using three balun transformers is shown in figure 8. this clock interface circuit pro- vides symmetric and balanced clock signals for frequencies up to the maximum update rate of the MAX19692. an equivalent circuit model for the clock inputs is shown in figure 9. clock duty cycle the duty cycle of the converter clock should be close to50%. if an ac-coupled sine-wave clock is used, the clock duty cycle is automatically close to 50%. if a square- wave clock is used, this is not necessarily the case. keeping the clock duty cycle close to 50% is particularly important when operating in rz and rf modes. when operating in rz mode, clock duty-cycle deviation from 50% distorts the converter s frequency response. a clock duty cycle above 50% increases the convert-er s output power at low frequencies, and lowers the frequency of the zero in the frequency response func-tion effectively producing a frequency response between that of nrz and rz modes.when operating in rf mode, a clock duty cycle higher or lower than 50% increases the output amplitude at low fre- quencies in the first nyquist zone and slightly lowers the output amplitude in the second and third nyquist zones. data inputs data inputs (dap[11:0], dan[11:0], dbp[11:0],dbn[11:0], dcp[11:0], dcn[11:0], ddp[11:0], ddn[11:0]) have lvds receivers followed by edge- triggered flip flops. four 12-bit buses accept data in offset binary format. the lvds inputs feature on-chip termination with differential 100 resistors. a 1.25v common-mode level with a ?00mv differential swingcan be applied to these inputs. see figure 10 for an equivalent circuit of the lvds inputs. single-ended clock input mini-circuits tc1-1-13m mini-circuits tc1-1-13m mini-circuits tc1-1-13m 50 50 100pf clkp clkn 100pf figure 8. clock application circuit with improved symmetry 100nf100nf mini-circuits tc1-1-13m 50 50 100 5k 5k +0.6v MAX19692 clkpclkn figure 7. typical clock application circuit downloaded from: http:///
MAX19692 12-bit, 2.3gsps, multi-nyquist dac with selectable frequency response ______________________________________________________________________________________ 17 data-timing relationships the timing of the lvds inputs is defined with respect tothe lvds output dataclk (dataclkp - dataclkn). the lvds data inputs are latched at 1/4 the input clock frequency. the dataclk output frequency is divided by another factor of 4 (clkdiv = 0) or by 2 (clkdiv = 1). define the 0 point of dataclk as the rising edge. for the case of clkdiv = 1, data are latched at 0 and 180 of dataclk, and setup and hold times must be satisfied for both these points in time. for the case of clkdiv = 0, data are latched at 0 , 90 ? 180 , and 270 of dataclk. setup and hold times must be satisfied for all four of these points in time. a delay set by the delay pin can skew dataclk by 1/2 period of the input data period, as shown in figure 11. this eases interfacing to an fpga where the clock to q delay of the lvds outputs is not adjustable. the clock driving the data input register is not delayed with the delay pin. the setup and hold times are always referred to the case when delay = 0. data-timing rela- tionships are shown in figure 12. d_p d_n 0.05 0.05 1.2nh1.2nh 0.1 106 0.1 0.03pf 1.2pf 1.2pf 1.75nh1.75nh k = 0.25 coupling factor k = 0.47 coupling factor d to 4:1 multiplexer k clk clock figure 10. lvds input equivalent circuit 0.1 100 5k 5k 10k 5k 100 100 0.1pf 0.1pf 1.0pf 0.05pf clkp clkn 0.1pf 0.1pf 2.7nh av clk 0.1 1.0pf 2.7nh figure 9. clock input equivalent circuit downloaded from: http:///
MAX19692 12-bit, 2.3gsps, multi-nyquist dac with selectable frequency response 18 ______________________________________________________________________________________ dataclk (clkdiv = 1) dap[11:0], dan[11:0]dbp[11:0], dbn[11:0] dcp[11:0], dcn[11:0]ddp[11:0], ddn[11:0] clkp, clkn dataclk (clkdiv = 0) dap[11:0], dan[11:0]dbp[11:0], dbn[11:0] dcp[11:0], dcn[11:0]ddp[11:0], ddn[11:0] clkp, clkn a) dual-data-rate interface b) quad-data-rate interface t s t h t s t h t s t h t s t h t s t h t s t h figure 12. setup (t s ) and hold time (t h ) for data input interface dataclk (delay = 0) dataclk (delay = 1) dataclk (delay = 0) dataclk (delay = 1) clkp, clkn (a) clkdiv = 1(b) clkdiv = 0 figure 11. effect of setting delay = 1 on data clock output downloaded from: http:///
MAX19692 12-bit, 2.3gsps, multi-nyquist dac with selectable frequency response ______________________________________________________________________________________ 19 applications information differential coupling using rf transformers the differential voltage existing between outp andoutn can be converted to a single-ended voltage using a transformer or a differential amplifier configuration. using a differential transformer-coupled output, in which the output power is limited to -2.6dbm, can optimize the dynamic performance. it is recommended that the dac outputs are pulled up to 3.3v. the use of bias tees, as shown in figure 13, is recommended for optimal perfor- mance. rf chokes can be used rather than bias tees if an isolation transformer is used. not pulling up the outputs to 3.3v is also possible, but may result in some degradation of dynamic performance in some applications. two out- put circuits are shown in figure 13. the circuit shown in figure 13(a) has less than 3db loss (in addition to the sinc attenuation built into the dac) from approximately 4mhz to 700mhz. the circuit shown in figure 13(b) that is used on the MAX19692 evaluation kit has less than 3db loss at frequencies up to approximately 1150mhz.to achieve the maximum bandwidth, it is important to minimize the inductance in the ground lead on the sec- ondary side of the transformers. it is recommended to use a very short trace and multiple vias for the connection to the ground plane. data synchronization the dac clock is running at four times the data rate ofthe data interface to the MAX19692. an lvds level data clock output (dataclkp, dataclkn) is provid- ed to help the user synchronize the data source and the dac. the output data clock frequency can be set to 1/2 the input data rate or 1/4 the input data rate. when the dac is running at full speed, this allows the data clock to be interfaced directly to fpgas without using an external clock divider. for example, if the dac is updating at 2.3gsps, the input data rate is 575mwps. if the dac is interfaced to an fpga, one could run the data clock at 1/4 the data input rate; hence the data output clock frequency would be 143.75mhz. 50 single-endedoutput mini circuits tc1-1-13m mini-circuits tcbt-2r5g av dd3.3 mini-circuits tcbt-2r5g av dd3.3 outp outn MAX19692 50 single-ended output sprague goodman glsw4m202 mini-circuits tcbt-2r5g av dd3.3 mini-circuits tcbt-2r5g av dd3.3 outp outn MAX19692 (a)(b) figure 13. possible output circuits for MAX19692 f clk f clk (a) (b) lvds data lvds data data source (fpga/asic) dac dataclk 4:1 mux output register out f clk / n* MAX19692 low-phase-noise pll system clock f clk / n* *n = 8 or n = 16 as set by clkdiv. data source (fpga/asic) dac dataclk 4:1 mux output register out f clk / n* MAX19692 phase det vco figure 14. data source to dac interfacing downloaded from: http:///
MAX19692 12-bit, 2.3gsps, multi-nyquist dac with selectable frequency response 20 ______________________________________________________________________________________ if the system clock is running at the dac update rate, the scheme in figure 14(a) can be used. in this case, the system is clocked using the data clock output from the dac. the delays of the data and the clock depend upon line lengths and loading. hence, clock deskewing using a phase-locked loop may be necessary to make this sys- tem work properly at speed. when clkdiv = 0, the data clock output can be phase-shifted by 45 using the delay pin. when clkdiv = 1, the data clock output canbe phase-shifted by 90 using the delay pin. an alternative solution is shown in figure 14(b). in thiscase, the system clock distribution is running at the data clock rate. a low-jitter, low-phase-noise phase- locked loop is used to generate the high-speed dac clock. using the data clock for feedback into the pll ensures synchronization between data and clock. if more than one MAX19692 is used in a system, and the relative phases need to be defined, the divided data clock of each dac should be phase locked to a system clock running at data-rate / 4 or data-rate / 2, which is equal to the input clock rate divided by 8 or 16. grounding, bypassing, power-supply, and board layout considerations grounding and power-supply decoupling can stronglyinfluence the performance of the MAX19692. unwanted digital crosstalk may couple through the input, refer- ence, power supply, and ground connections, affecting dynamic performance. proper grounding and power- supply decoupling guidelines for high-speed, high-fre- quency applications should be closely followed. this reduces emi and internal crosstalk that can significantly affect the dynamic performance of the MAX19692. use of a multilayer pc board with separate ground and power-supply planes is required. it is recommended that the analog output and the clock input are run as controlled-impedance microstrip lines on the top layer of the board, directly above a ground plane, and that no vias are used for the clock input (clkp, clkn) and the analog output (outp, outn) signals. depending on the length of the traces, and the operating condition, a low-loss dielectric material (such as rogers ro4003) as the top layer dielectric may be advisable. the data clock (dataclkp, dataclkn) must be rout- ed so its coupling into the clock input and the dac output is minimized. digital input signals should be run as controlled-imped- ance strip lines between ground planes. digital signals should be kept as far away from sensitive analog inputs, reference input sense lines, common-mode inputs, and clock inputs as practical. it is particularly important to minimize coupling between digital signals and the clockto optimize dynamic performance for high output fre- quencies. a symmetric design of the clock input and analog output lines is critical to minimize distortion and optimize the dac s dynamic performance. digital signal paths should be kept short and runlengths matched to avoid propagation delay and data- skew mismatches. the MAX19692 supports three separate power-supply inputs for analog 3.3v (av dd3.3 ), switching (v dd1.8 ), and clock (av clk ) circuits. each av dd3.3 , v dd1.8 , and av clk input should at least be decoupled with a sepa- rate 47nf capacitor as close to the pin as possible andtheir opposite ends with the shortest possible connec- tion to the corresponding ground plane, to minimize loop inductance. all three power-supply voltages should also be decoupled at the point they enter the pc board with tantalum or electrolytic capacitors. ferrite beads with additional decoupling capacitors forming a pi-network could also improve performance. the power-supply inputs v dd1.8 and av clk of the MAX19692 allow a 1.8v ?.1v supply voltage range forupdate rates < 2.0gsps. a range of 1.8v to 1.9v should be used for 2.0gsps to 2.3gsps. the analog power- supply input av dd3.3 allows a 3.3v ?.2v supply volt- age range. to optimize the dynamic performance of theMAX19692 over temperature at the highest update rates, it is important that the difference between v dd1.8 and av dd3.3 is at least 1.4v. if v dd1.8 is 1.9v and av dd3.3 is 3.1v, dynamic performance at these update rates will degrade at higher temperatures, as shown inthe typical operating characteristics . the MAX19692 is packaged in a 169 csbga packagewith 0.8mm ball pitch (package code: x16911-1) , provid- ing design flexibility, thermal efficiency, and a small foot-print for the dac. static performance parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on anactual transfer function from either a best straight-line fit (closest approximation to the actual transfer curve) or end-point fit (a line drawn between the end points of the transfer function, once offset and gain errors have been nullified). for a dac, the deviations are measured at every individual step. the MAX19692 inl is specified using the end-point method. downloaded from: http:///
differential nonlinearity (dnl) differential nonlinearity is the difference between an actu-al step height and the ideal value of 1 lsb. a dnl error specification greater than -1 lsb guarantees a monotonic transfer function. offset error the offset error is the difference between the ideal andthe actual offset current. for a dac, the offset point is the average value at the output for the two midscale digital input codes with respect to the full scale of the dac. this error affects all codes by the same amount. gain error a gain error is the difference between the ideal and theactual full-scale output voltage on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corresponds to the same percent- age error in each step. dynamic performance parameter definitions settling time the settling time is the amount of time required from thestart of a transition until the dac output settles its new output value to within the specified accuracy. noise spectral density the dac output noise is the sum of the quantization noiseand other noise sources. noise spectral density is the noise power in a 1hz bandwidth. spurious-free dynamic range (sfdr) sfdr is the ratio of the rms amplitude of the carrier fre-quency (maximum signal components) to the rms value of the largest distortion component. sfdr is usually mea- sured in dbc with respect to the carrier frequency ampli- tude or in dbfs with respect to the dac s full-scale range. depending on its test condition, sfdr is observedwithin a predefined window or to nyquist. two-/four-tone intermodulation distortion (imd) the two-/four-tone imd is the ratio expressed in dbc (ordbfs) of the worst 3rd-order (or higher) imd products to any output tone. MAX19692 12-bit, 2.3gsps, multi-nyquist dac with selectable frequency response ______________________________________________________________________________________ 21 downloaded from: http:///
MAX19692 12-bit, 2.3gsps, multi-nyquist dac with selectable frequency response 22 ______________________________________________________________________________________ MAX19692 1 234 56 7891 01 11 21 3 fsadj dacref av dd3.3 refio top view a1 f1 e1 d1 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 l1 l2 l3 l4 l5 l6 l7 l8 l9 l10 l11 l12 l13 k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 k11 k12 k13 j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 j11 j12 j13 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 e2 e3 e4 e5 e6 e7 e8 e9 e10 e11 e12 e13 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 g12 g13 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 ab c d cref refres rz rf gnd cal v dd1.8 v dd1.8 gnd gnd gnd gnd gnd e f v dd1.8 v dd1.8 v dd1.8 v dd1.8 dap7 dap6 dap8 dap9 av dd3.3 outp gnd gnd gnd gnd gnd gnd dap10 dap11 g h j dan7 dan6 dan8 dan9 dan10 dap0 dap1 dap2 dap3 dan0 dan1 dan2 dan3 k l dbp11 dbp10 dbp9 dbp8 dbn11 dbn10 dbn9 dbn8 dan11 dap4 dap5 dan4 dan5 dbp3 dbp1 dbn3 dbn1 m n dbp7 dbp6 dbp5 dbp4 dbp2 dbn7 dbn6 dbn5 dbn4 dbp0 dbn2 dbn0 av dd3.3 outn av dd3.3 gnd gnd gnd v dd1.8 gnd gnd gnd gnd gnd gnd gnd gnd gnd ddn11 ddn0 ddn1 v dd1.8 gnd v dd1.8 gnd gnd gnd v dd1.8 v dd1.8 ddn2 ddn3 ddp11 ddp0 ddp1 ddp2 ddn10 ddn5 ddn6 ddp10 ddp5 ddp6 dcp10 dcp8 dcp3 dcn10 dcn8 dcn3 ddp3 ddn7 ddn8 ddp7 ddp8 dcp2 dcp1 dcn2 dcn1 dcp11 dcp9 dcp7 dcp6 dcn11 dcn9 dcn7 dcp5 dcn6 dcn5 av clk av clk clkn av clk av clk v dd1.8 ddn4 gnd gnd gnd clkp gnd v dd1.8 v dd1.8 ddp4 gnd ddn9 ddp9 dcn0 dcp0 dataclkn dataclkp delay clkdiv dcp4 gnd dcn4 n.c. pin configuration the MAX19692 is packaged in an 11mm x 11mm, 169 csbga package (package code x16911-1). ball pitch is 0.8mm. downloaded from: http:///
MAX19692 12-bit, 2.3gsps, multi-nyquist dac with selectable frequency response maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 23 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. 169l csbga.eps a 1 1 21-0165 package outline169l csbga, 11x11x1.4mm package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) downloaded from: http:///

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